With the aggressive growth of battery powered portable electronics (e.g., cell phones), the demand for low cost and better efficiency battery chargers is extremely high. Flyback converter is the first choice among different switching mode topologies to meet this demand due to its simplicity. Over the years, various primary-side regulated Pulse Width Modulation (PWM) or Pulse Frequency Modulation controller integrated circuit chips have been developed and used to build constant voltage Flyback power supplies.
FIG. 1. A shows a block diagram of an exemplary prior-art primary-side controlled PFM converter. Such a primary-side controlled PFM converter typically comprises a full bridge rectifier 107, a transformer T1 (including three windings: primary winding 101, secondary winding 102 and auxiliary winding 103), a primary switch 105, a primary-side regulated PFM controller 100, an auxiliary power supply network 108, a secondary rectifier D1 and an output capacitor C1. A resistor 109 and a capacitor C2 provide the initial start-up energy for the primary-side regulated PFM controller 100. Once the primary-side controlled PFM converter is stable, primary-side regulated PFM controller 100 is powered by the auxiliary power network 108. The output voltage is fed back to the primary winding 101 via the auxiliary winding 103 and sensed by voltage divider resistor R2 and R3. A resistor Rcs senses the current flowing through primary switch 105. The primary switch peak current Ipkp against with output loading is a constant and its characteristic curve I1 is depicted in FIG. 10.
A functional block diagram of the primary-side regulated PFM controller is shown in FIG. 1B. It consists of a current sense comparator 111, a feedback error amplifier 112, constant voltage (CV) control module 113 and PFM control module 115. Voltage at CS node which represents the current magnitude of primary winding 101 is coupled to the positive input of the CS comparator 111 and compared with an internal reference voltage VCS0. The CS comparator 111 becomes high while the CS node voltage reaches the reference voltage VCS0 to turn off the primary switch 105. During the off time, the feedback error amplifier module 112 samples the VFB voltage signal through the resistor divider networks R2 and R3. The result of the error amplifier 112 is coupled to the CV control module 113 which is used for setting primary switch 105 off time. A negative feedback control loop is formed by auxiliary winding with secondary to auxiliary winding ratio NSA, divider network R2 and R3, error amplifier 112, CV control module 113, PFM control module 115 and primary switch 105 which sets the output voltage defined by equation (1);
                              V          o                =                                            V                              REF                ⁢                                                                  ⁢                0                                      ⁢                                                            N                  SA                                ×                                  (                                                            R                      2                                        +                                          R                      3                                                        )                                                            R                3                                              -                      V                          D              ⁢                                                          ⁢              1                                                          (        1        )            
FIG. 2 illustrates the operation principle of the prior-art primary-side controlled PFM converter shown in FIG. 1A. Waveform “OUT” shown in FIG. 2 is the output control signal 106 from the primary-side regulated PFM controller 100 shown at FIG. 1. This output control signal 106 drives the primary switch 105 on and off. During the on time, the primary winding current Ip is increasing with time at a positive slope which is defined by Vin/LP. Energy is then stored in the primary side inductor with inductance value LP of the transformer T1 but not transferred to the output loading. While the primary winding current IP hits a reference value Ipkp which is defined by VCS0/RCS, the output of the CS comparator 111 turns high that instructs PFM control module 115 to turn off the primary switch 105. Once the primary switch 105 is off, the secondary rectifier D1 becomes forward bias and a secondary current IS starting with peak value Ipks flows through the secondary rectifier D1. IS is decreasing with time duration Tons at a negative slope VS/LS where LS is the inductance of secondary side. By considering the Is waveform shown in FIG. 2, load output current Io can be expressed as:
                              I          o                =                                            1              2                        ⁢                          I              pks                        ⁢                                          T                ons                            T                                =                                    1              2                        ⁢                          I              pks                        ⁢            F            ⁢                                                  ⁢                                                            L                  S                                ⁢                                  I                  pks                                                            V                S                                                                        (        2        )            
Re-arrange equation (2), switching frequency F (1/T) of the primary switch 105 can be expressed as:
                    F        =                                            2              ⁢                              V                S                                                                    L                S                            ⁢                              I                pks                2                                              ⁢                      I            O                                              (        3        )            
As Ipkp, VS, NPS and LS are a constant value in the traditional primary-side regulated PFM controller 100, the switching frequency F of the primary switch 105 is direct proportional to load output current IO. Its frequency against output loading characteristic curve F1 is depicted in FIG. 8.
The advantage of using constant Ipkp is its simplicity of circuit implementation for frequency reduction and cable compensation scheme which is in turns to have minimum die cost. However, it may have audible noise at light load condition while the switching frequency drops into 1˜2 KHz frequency range which is the most sensitive frequency range for human ear. Another issue by using this scheme is the poor transient response from light to heavy load transition. This is because the switching frequency becomes too low (e.g. 500 Hz) at no load condition to response any sudden change of loading that incurs high output voltage dip.